This application is related to:
U.S. patent application Ser. No. 09/978,859, now U.S. Pat. No. 6,545,906, entitled xe2x80x9cA Method of Writing to a Scalable Magnetoresistance Random Access Memory Element,xe2x80x9d filed Oct. 16, 2001, and assigned to the assignee hereof;
U.S. patent application Ser. No. 10/186,141, entitled xe2x80x9cCircuit and Method of Writing a Toggle Memory,xe2x80x9d filed simultaneously herewith, and assigned to the assignee hereof;
U.S. patent application Ser. No. 10/185,868, entitled xe2x80x9cMRAM Architecture With Electrically Isolated Read and Write Circuitry,xe2x80x9d filed simultaneously herewith, and assigned to the assignee hereof;
U.S. patent application Ser. No. 10/185,888, entitled xe2x80x9cMemory Architecture With Write Circuitry and Method Therefor,xe2x80x9d filed simultaneously herewith, and assigned to the assignee hereof; and
U.S. patent application Ser. No. 10/185,488, entitled xe2x80x9cMemory Having A Precharge Circuit and Method Therefor,xe2x80x9d filed simultaneously herewith, and assigned to the assignee hereof.
1. Field of the Invention
This invention relates to Magnetoresistive Random Access Memories (MRAMs), and more particularly to architectures for MRAMs.
2. Background of the Invention
Non-volatile memory devices, such as FLASH memories, are extremely important components in electronic systems. FLASH is a major non-volatile memory device in use today. Disadvantages of FLASH memory include high voltage requirements and slow program and erase times. Also, FLASH memory has a poor write endurance of 104-106 cycles before memory failure. In addition, to maintain reasonable data retention, the scaling of the gate oxide is restricted by the tunneling barrier seen by the electrons. Hence, FLASH memory is limited in the dimensions to which it can be scaled.
To overcome these shortcomings, magnetic memory devices are being evaluated. One such device is magnetoresistive RAM (hereinafter referred to as xe2x80x9cMRAMxe2x80x9d). To be commercially practical, however, MRAM must have comparable memory density to current memory technologies, be scalable for future generations, operate at low voltages, have low power consumption, and have competitive read/write speeds.
For an MRAM device, the stability of the nonvolatile memory state, the repeatability of the read/write cycles, and the memory element-to-element switching field uniformity are three of the most important aspects of its design characteristics. A memory state in MRAM is not maintained by power, but rather by the direction of the magnetic moment vector. Storing data is accomplished by applying magnetic fields and causing a magnetic material in a MRAM device to be magnetized into either of two possible memory states. Recalling data is accomplished by sensing the resistive differences in the MRAM device between the two states. The magnetic fields for writing are created by passing currents through strip lines external to the magnetic structure or through the magnetic structures themselves.
As the lateral dimension of an MRAM device decreases, three problems occur. First, the switching field increases for a given shape and film thickness, requiring a larger magnetic field to switch. Second, the total switching volume is reduced so that the energy barrier for reversal decreases. The energy barrier refers to the amount of energy needed to switch the magnetic moment vector from one state to the other. The energy barrier determines the data retention and error rate of the MRAM device and unintended reversals can occur due to thermofluctuations (superparamagnetism) if the barrier is too small. A major problem with having a small energy barrier is that it becomes extremely difficult to selectively switch one MRAM device in an array. Selectablility allows switching without inadvertently switching other MRAM devices. It is. important to control the current flowing during a write operation in the array to avoid undesired current surges or spikes during transistor switching.
Finally, because the switching field is produced by shape, the switching field becomes more sensitive to shape variations as the MRAM device decreases in size. With photolithography scaling becoming more difficult at smaller dimensions, MRAM devices will have difficulty maintaining tight switching distributions. In any memory type, including MRAMs, there is a continuing desire to reduce the memory size and increase performance. One important aspect of performance is the speed with which the memory is read and programmed (written). Speed limitations include such things as the performance of the bit cell and the capacitance of the lines running through the array. A variety of techniques have been developed to improve these characteristics. For example, memory arrays have commonly been divided into subarrays so that no single line is excessively capacitive. This can also reduce power consumption. It is important in memories to efficiently switch the write circuitry to allow the write cycle speed to approximate the read cycle speed. The inability of a FLASH to accomplish this objective is a major disadvantage of FLASH.
The promise of MRAMs is, however, that of a universal memory that can be high speed and non-volatile. Thus, the need for improvements in speed and memory area efficiency continue. Thus, there is need for further improvements in architecture for MRAMs.